1. Technical Field
The present disclosure relates to high frequency RF divider circuits.
2. Background Information
In many applications dividers that generate In-phase (I) and Quadrature (Q) signals are desired. FIG. 1 (Prior Art) is a diagram of a divide-by-two circuit 1. Circuit 1 includes two latches 2 and 3 that are interconnected to form a toggle flip-flop. The input clock signal is a differential signal, denoted here as involving signals VOP and VON. The I output signal is a differential output signal involving signals IP and IN. The Q output signal is also a differential output signal involving signals QP and QN. The I and Q signals are ninety degrees out of phase with respect to one another. There are several known ways to realize the latches 1 and 2 of FIG. 1.
FIG. 2 (Prior Art) is a diagram of a divider of the type of FIG. 1, realized using CML (Common Mode Logic) latches. FIG. 3 (Prior Art) is a diagram of a complementary logic latch 4 of a type usable in the divide-by-two circuit of FIG. 1. “Complementary logic”, which refers to logic circuitry involving both P-channel and N-channel transistors, is often more commonly referred to as CMOS (Complementary Metal Oxide Semiconductor) logic even though the transistors making up the logic circuitry may not have metal gates and may not have oxide gate dielectrics. FIG. 4 (Prior Art) is a diagram of another type of complementary logic latch 5 usable to realize the latches of the divider of FIG. 1.
Each of the latches of FIG. 2, FIG. 3 and FIG. 4 has its advantages and disadvantages in terms of maximum operating frequency, implementation size, rail-to-rail output voltage swing operation, output signal noise, minimum supply voltage, and power consumption. For example, the CML latch example of FIG. 2 is operable at a 10 GHz input clock frequency and at relatively low supply voltages and is therefore often preferable in a high speed divider application in a cellular telephone local oscillator. The circuit, however, unfortunately consumes a large amount of supply current in a range of approximately 12 milliamperes. To prevent the divider from introducing too much noise for the cellular telephone application mentioned above, the pullup load resistances 6-9 are made small. In the illustrated example, the pull-up load resistances 6-9 are 200 ohms. Due to the small pullup load resistances, however, the pull-down transistors 10-19 are generally sized larger to provide adequate current flow over resistances 6-9 such that the divider will output signals having adequate output signal voltage swings. The complementary logic latch circuit of FIG. 3 also has disadvantages. For example, when the inverter involving transistors 20 and 21 is enabled and is to switch, the output signal current must flow through the on-resistances of enable transistors 22 and 23. Voltage drops across these enable transistors limit low supply voltage operation of the circuit. To reduce the on-resistance of the enable transistors, the transistors are generally made larger if high operating speed is required and if low supply voltage operation is required. The latch of FIG. 4 is even larger and slower than the latch of FIG. 3. Moreover, due to the many switching logic elements, the latch of FIG. 4 consumes an undesirably large amount of supply current when operating at high frequencies.